Graduate Students

Michael Clavel
Email: mbclavel[at]vt[dot]edu
Education:
M. S. , Virginia Tech, December 2015
B.S., Electrical Engineering, Virginia Polytechnic Institute and State University, 2013
MS Thesis Title:
"Tensile-Strained Ge/InxGa1-xAs Heterostructures for Electronic and Photonic Applications"
Research:
Michael is interested in the study of novel strain and bandgap engineered Ge/InGaAs heterojunction low-power tunnel transistors heterogeneously integrated on GaAs and Si for lower power CMOS logic.
Hobbies: Michael enjoys astronomy, hiking, jogging, and playing electric guitar.

Jheng-Sin Liu
Email: jsliu[at]vt[dot]edu
Education:
M. S. ,Graduate Institute of Photonics and Optoelectronics,National Taiwan University,Taiwan, 2013
B.S., Electrical Engineering, National Tsing Hua University,Taiwan,2011
Research:
Jheng is interested in modelling and the MBE growth of mixed arsenide/antimonide based tunnel field effect transistors heterogeneously integrated on Si for ultra-low power logic applications.
Hobbies: Jheng enjoys jogging and cooking.

Sarat Saluru
Email: sarks93[at]vt[dot]edu
Education:
B. E. , Electronics and Communication Engineering, People's Education Society University, Bangalore, 2015
Research:
Sarat is interested modelling and fabrication of InGaAs based FinFET devices on Silicon for post-Si CMOS applications.
Hobbies: Sarat enjoys food, travelling and fitness.



Aheli Ghosh
Email: gaheli3[at]vt[dot]edu
Education:
B.E. , Instrumentation and Electronics Engineering, Jadavpur University, Kolkata, 2015
Research:
Aheli is interested III-V Multijunction Solar Cells on Si Substrate via Ge and GaAsSb dislocation filtering buffers: Cell Design, Epitaxial Growth & Fabrication.
Hobbies: Aheli enjoys trekking, travelling, food and psychology.

Sanal Khan
Email:
Education:
M. S.



Shuvodip Bhattacharya
Email:
Education:
M. S.




Undergraduate Student

Yingying Gui
Email: gyingy3[at]vt[dot]edu
Education:
B. S. , Electrical Engineering, Virginia Polytechnic Institute and State University, 2016
Research:
Yingying is interested in Evaluating Mixed Arsenide/Antimonide MOS Interfaces for Low-Power Electronics.
Hobbies: Yingying enjoys travelling.


ADSEL Alumni (Currently Pursuing Higher Studies or Working in Industry)
Peter D. Nguyen
Email: petern[at]vt[dot]edu
Education:
M. S. , Virginia Tech, May 2016
B.S., Electrical Engineering, Virginia Polytechnic Institute and State University, 2014
MS Thesis Title:
"Heteroepitaxial Ge on Si via High-Bandgap III-V Buffers for Low-Power Electronic Applications"

Peter will be joining at Intel Corporation, Portland, OR as a Process Engineer.
Patrick Goley
Email: patrick[dot]goley[at]vt[dot]edu
Education:
M. S. , Virginia Tech, July 2015
B.S., Electrical Engineering, Virginia Polytechnic Institute and State University, 2013
MS Thesis Title:
"Plastic Relaxation of Highly Tensile Strained (100) Ge/InGaAs Heterostructures"

Patrick is currently working towards his PhD degree @ Georgia Tech.
Nikhil Jain
Graduate Students
Email: jain34[at]vt[dot]edu
Education:
Ph. D. , Virginia Tech, March 2015
B.S., University of Illinois at Urbana Champaign, 2010
MS Thesis title:
"Design of III-V multijunction solar cells on Si substrate"
PhD Thesis Title:
"Heterogeneous Integration of III-V Multijunction Solar Cells on Si Substrate: Cell Design & Modeling, Epitaxial Growth & Fabrication"

Nikhil is currently working as a Postdoctoral Researcher at National Renewable Energy Laboratory (NREL), CO.
Yan Zhu
Email: zhuyan[at]vt[dot]edu
Education:
Ph. D. , Virginia Tech, April 2014
M.E., Institute of Semiconductors, Chinese Academy of Sciences, China, 2011
B.S., School of Physics, Shandong University, China, 2008
PhD Thesis Title:
"Mixed As/Sb and tensile strained Ge/InGaAs heterostructures for low-power tunnel field effect transistors (TFETs)"

Yan is currently working as a Device Engineer at Toshiba Corporation of America, Livermore, CA.
Siddharth Vijayaraghavan
Email: svijayar[at]vt[dot]edu
Education:
M. Engineering , Virginia Tech, 2012
M.S., University of Houston, 2009
B.E., Anna University, 2006
Project Report:
MBE lab set up, literature review, mask design and TEM sample preparation and imaging.

Siddharth is currently working for AMD, Austin, Texas.
Bipin Dhavale
Email: bipinpd[at]vt[dot]edu
Education:
M. Engineering , Virginia Tech, 2011
B.E., Visvesvaraya Technological University, 2003



Bipin is currently working for Altera Corporation, San Jose, California.
Patrick Goley
Email: patrick[dot]goley[at]vt[dot]edu
Education:
B. S. , Virginia Tech, 2013
UG Honors Thesis:
Electrical Characterization of Oxide-Semiconductor Interfaces.

Patrick is currently working towards his M. S. degree @ADSEL, Virginia Tech. Received NSF Graduate Research Fellowship 2013.
Peter Nguyen
Email: petern[at]vt[dot]edu
Education:
B. S. , Virginia Tech, 2014
UG Research:
Interface characterization of high-K dielectrics on InGaAs and Si MOS-C.

Peter is currently working towards his M. S. degree @ADSEL, Virginia Tech. Received NSF Graduate Research Fellowship 2014.
Krishna Neupane
Email: krishna1[at]vt[dot]edu
Education:
B. S. , Electrical Engineering, Virginia Polytechnic Institute and State University, 2013



Currently working at United States Patent and Trademark Office.

Usman Maqsood
Email:
Education:
B. S. , Virginia Tech, 2011
Summer Research:
Contact formation on III-V materials using Physical Vapor Deposition (PVD).

Currently working as a Power Electronics Design Engineer at Boeing, Saint Peters, Missouri.