New material innovations, novel device architectures and their heterogeneous integration onto Si substrates are required to continue the transistor miniaturization. Beyond sub 22nm technology node, high mobility low-bandgap III-V compound semiconductor materials have the potential to provide much higher switching speeds and to operate at much lower voltage than silicon based devices. Therefore, there is a renewed interest in exploring new device architectures using ultra-high mobility quantum-well field-effect transistors (QWFETs) on Si for future generation of high-performance and ultra-low power applications. We envision complementing Si CMOS with novel semiconductor materials with tunable band structure, tailored optoelectronic and photonic properties.
The goal of our program is to achieve a viable n-channel and p-channel mixed-anion and mixed-cation III-V materials and device architecture integration strategy onto non-patterned and patterned Si via careful materials science as applied to heteroepitaxy, defect suppression, strain and bandgap engineering to achieve higher quantum-well mobilities. The lower defect density along with lower processing temperature to obtain higher mobility in QWFET on Si without the parasitic, parallel conduction to the active channel using MBE is one of the major impediments in this research. Throughout the effort, significant emphasis will be made on the identification of defect types and their relation to variation in growth conditions, buffer characterization, QW mobility, precise group-V composition control and benchmarking so that guidelines toward a robust methodology for high-performance III-V QW devices on Si are established.
In order to scale the CMOS circuits below 22nm technology node, development of p-channel quantum-well FETs using new materials and new device architectures is an important goal. Although strained III-Sb and III-As material systems are widely studied in p-channel materials, bulk transport properties of Ge makes it the main candidate for p-channel option particular for deeply scaled devices. We are investigating Ge quantum-well field-effect transistor architectures using in-situ growth process utilizing separate Ge and III-V MBE growth chambers.
With continued scaling of silicon CMOS technology, each transistor becomes smaller, faster, and cheaper, leading to unprecedented increase in microprocessor performance. However, the rising gate count on a single chip also increases the power consumption. Hence, the conventional device scaling and performance enhancing concept is encountered with several limitations. These now require a trade-off among observables such as on-current, power consumption, off-state leakage current and short channel effects. New materials innovation and device structure engineering are needed to lower power consumption and enhance performance of microprocessor technology at both discrete transistor and architectural level. Introduction of high mobility compound semiconductor III-V channel materials and multi-gate structure are required for providing both high drive current and well-controlled short channel effects. Low bandgap III-V based quantum well field effect transistor architecture have been proposed as a promising device option because of its high-speed switching at very low supply voltages, due to its excellent transport properties. However, current Si based CMOS logic devices enjoy the enormous, efficient and comparably inexpensive manufacturing infrastructure that have been developed over a few decades. Hence, rather than attempting to replace Si CMOS, III-V materials and device structures need to be heterogeneously and selectively integrated on Si substrate in order to take the advantage of their superior transport properties. This avoids the difficult, expensive and large-disruption of replacing main-stream, large size Si wafer by III-V substrates.
Our approach of heteroepitaxial, monolithic integration of compound semiconductor based materials and devices on Si substrate requires a single wafer to achieve a finished chip differs from other integration schemes such as, bonding, III-V on SOLES (semiconductor on lattice engineered substrate), aspect ratio trapping, PDMS (polydimethylsiloxane) epitaxial transfer, and flip-chip, etc. This eliminates costly device transfer, wafer bonding and assembly steps. Moreover, our heterogeneous integration strategy not only enables us to achieve high-density III-V devices on Si but also opens up new avenues of incorporating III-V based optoelectronic devices on Si platform. Thus, the ultimate goal of our research is to fulfill the marriage of III-V compound semiconductor devices with Si CMOS chips for logic, detectors, lasers, modulators, and interconnect applications.
Development of tunnel field-effect transistors (TFETs) using new materials and new device architectures is an important goal to provide a further scaling of CMOS circuits. One of the most promising approaches is to reduce the power supply voltage by using a novel device, tunnel FET which operates by tunnel injection of carriers from source to channel, rather than thermionic emission and thus enables to achieve sharp turn-on characteristics of a transistor. Although several tunnel FET designs including III-V homojunction, heterojunction staggered-gap and broken-gap were recently reported in the literature to increase the (i) ON-state current, (ii) low OFF- state leakage and (iii) subthreshold slope, S<60mV/dec only in a narrow gate voltage range; however, very limited experimental demonstration of III-V staggered and broken-gap structures are available to-date. The design would require proper selection of the source and the channel materials as well as the materials growth compatibilities of the mixed-anion and mixed-cation based materials system for high-performance tunnel FET devices.
Our group is investigating the device physics and is developing experimentally, low-bandgap III-V staggered and broken-gap n and p-channel III-V tunnel heterojunction diodes and transistors including mixed-cation and mixed-anion by MBE.
With looming energy crisis across the globe, photovoltaics technology proposes a promising clean and green renewable source of energy. Currently, a desirable widespread use of photovoltaics over other energy sources is prevented by the relatively higher cost. Therefore, there is an immediate need not only to increase the efficiency but also to make the technology affordable by making thin film solar cells. Our group is exploring the heteroepitaxial growth of III-V compound semiconductor materials for photovoltaic applications.
Our main focus is to develop tandem solar cell structure onto germanium (Ge) and silicon (Si) substrate that would incorporate strain compensated (III-V)-based (i) quantum wells (QWs) and (ii) quantum dots (QDs) structures. These low-dimensional semiconductor materials when inserted in the intrinsic region of the host cell would enable higher efficiencies. Significant challenges namely i) lower defect density, ii) higher minority carrier lifetime, iii) current matching of each cell, iv) highly doped tunnel junction for carrier collection, and v) lower overall processing and materials cost per watt needs to be solved prior to realization of the high efficiency solar cells on cheaper Si substrate.
Present day traditional energy generation technologies are not only facing crisis and but are also posing serious environmental threat. Including concerns with climate change and fossil fuel shortage, we need to develop alternative sources of renewable energy. Thermophotovoltaic (TPV) energy conversion is a direct thermal-to-electric energy conversion process whereby an emitter or radiator is heated to incandescence and a photovoltaic device is placed in view of the emitter. The conversion of thermal-to-electric energy is in the temperature range from 1000K to 1500K is a clean method for producing electricity that does not produce any (net) carbon dioxide emission.
We propose to develop a monolithic integrated module of low bandgap, III-V thermophotovoltaic device structure for thermal energy conversion and sensing applications. We employ a novel combination of engineered substrate architecture that offers a much greater flexibility of monolithic device integration, material choice and ensures lower defect density to produce high-performance III-V TPV devices in the broadband emitter temperature of 1000K to 1500K.